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| Small Footprint PicoGuard XS(R) ESD Clamp Array For High Speed Data Line Protection CM1235 Features * * ESD protection for 4 pairs of differential channels ESD protection to: * IEC61000-4-2 Level 4 (ESD) at 8kV contact discharge * IEC61000-4-4 (EFT) 40A (5/50ns) * IEC61000-4-5 (Lighting) 3.5A (8/20s) Pass-through impedance matched clamp architecture Flow-through routing for high-speed signal integrity Minimal line capacitance change with temperature and voltage 100 matched impedance for each paired differential channel Each I/O pin can withstand over 1000 ESD strikes* RoHS compliant (lead-free), small footprint 4.0mm x 1.7mm TDFN-16 package Product Description The PicoGuard XS protection family is specifically designed for next generation deep sub-micron high speed data line protection. The CM1235 is ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading and tightly controlled signal skews (with channel-to-channel matching at 2% max deviation). The device is particularly well-suited for protecting systems using high-speed ports such as DisplayPort or HDMI, along with corresponding ports in removable storage, digital camcorders, DVD-RW drives and other applications where extremely low loading capacitance with ESD protection are required. The CM1235 also features easily routed "passthrough" pinouts in a RoHS compliant (lead-free), 4.0mm x 1.7mm, 16-lead TDFN, small footprint package. * * * * * * Applications * * DVI, DisplayPort, and HDMI ports in notebooks, set top boxes, digital TVs, LCD displays General purpose high-speed data line ESD protection (c)2010 SCILLC. All rights reserved. April 2010 - Rev. 3 Publication Order Number: CM1235/D CM1235 Block Diagram *Standard test condition is IEC61000-4-2 level 4 test circuit with each pin subjected to 8kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. PicoGuard XS ESD Protection Architecture Conceptually, an ESD protection device performs the following actions upon an ESD strike discharge into a protected ASIC (see Figure 1): 1. When an ESD potential is applied to the system under test (contact or air-discharge), Kirchoff's Current Law (KCL) dictates that the Electrical Overstress (EOS) currents will immediately divide throughout the circuit, based on the dynamic impedance of each path. 2. Ideally, the classic shunt ESD clamp will switch within 1ns to a low-impedance path and return the majority of the EOS current to the chassis shield/reference ground. In actuality, if the ESD component's response time (tCLAMP) is slower than the ASIC it is protecting, or if the Dynamic Clamping Resistance (RDYN) is not significantly lower than the ASIC's I/O cell circuitry, then the ASIC will have to absorb a large amount of the EOS energy, and be more likely to fail. 3. Subsequent to the ESD/EOS event, both devices must immediately return to their original specifications, and be ready for an additional strike. Any deterioration in parasitics or clamping capability should be considered a failure, since it can then affect signal integrity or subsequent protection capability. (This is known as "multistrike" capability.) Rev. 3 | Page 2 of 14 | www.onsemi.com CM1235 In the CM1235 PicoGuard XS architecture, the signal line leading the connector to the ASIC routes through the CM1235 chip which provides 100 matched differential channel characteristic impedance that helps optimize 100 load impedance applications such as the HDMI high speed data lines. Note:When each of the channels are used individually for single-ended signal lines protection, the individual channel provides 50 characteristic impedance matching. The load impedance matching feature of the CM1235 helps to simplify system designer's PCB layout considerations in impedance matching and also eliminates associated passive components. The route through the PicoGuard XS architecture enables the CM1235 to provide matched impedance for the signal path between the connector and the ASIC. Besides this function, this circuit arrangement also changes the way the parasitic inductance interacts with the ESD protection circuit and helps reduce the IRESIDUAL current to the ASIC. Figure 1. Standard ESD Protection Device Block Diagram Rev. 3 | Page 3 of 14 | www.onsemi.com CM1235 The PicoGuard XS Architecture Advantages Figure 2 illustrates a standard ESD protection device. The inductor element represents the parasitic inductance arising from the bond wire and the PCB trace leading to the ESD protection diodes. Figure 2. Standard ESD Protection Model Figure 3 illustrates a standard ESD protection device. The inductor element represents the parasitic inductance arising from the bond wire and the PCB trace leading to the ESD protection diodes. Figure 3. CM1234 PicoGuard XS ESD Protection Model Rev. 3 | Page 4 of 14 | www.onsemi.com CM1235 CM1235 Inductor Elements In the CM1235 PicoGuard XS architecture, the inductor elements and ESD protection diodes interact differently compared to the standard ESD model. In the standard ESD protection device model, the inductive element presents high impedance against high slew rate strike voltage, i.e. during an ESD strike. The impedance increases the resistance of the conduction path leading to the ESD protection element. This limits the speed that the ESD pulse can discharge through the ESD protection element. In the PicoGuard XS architecture, the inductive elements are in series to the conduction path leading to the protected device. The elements actually help to limit the current and voltage striking the protected device. First the reactance of the inductive element, L1, on the connector side when an ESD strike occurs, acts in the opposite direction of the ESD striking current. This helps limit the peak striking voltage. Then the reactance of the inductive element, L2, on the ASIC side forces this limited ESD strike current to be shunted through the ESD protection diodes. At the same time, the voltage drop across both series element acts to lower the clamping voltage at the protected device terminal. Through this arrangement, the inductive elements also tune the impedance of the ESD protection element by cancelling the capacitive load presented by the ESD diodes to the signal line. This improves the signal integrity and makes the overall ESD protection device more transparent to the high bandwidth data signals passing through the channel. The innovative PicoGuard XS architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the ESD current strike to the protected device and also improves the signal integrity of the system by balancing the capacitive loading effects of the ESD diodes. At the same time, this architecture provides an impedance matched signal path for 50 loading applications. Board designs can take advantage of precision internal component matching for improved signal integrity, which is not otherwise possible with discrete components at the system level. This helps to simplify the PCB layout considerations by the system designer and eliminates the associated passive components for load matching that is normally required with standard ESD protection circuits. Each ESD channel consists of a pair of diodes in series that steer the positive or negative ESD current pulse to either the Zener diode or to ground. This embedded Zener diode also serves to eliminate the need for a separate bypass capacitor to absorb positive ESD strikes to ground. The CM1235 protects against ESD pulses up to 8kV contact per the IEC 61000-4-2 standard. Rev. 3 | Page 5 of 14 | www.onsemi.com CM1235 PIN DESCRIPTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PAD Name In_1+ In_1In_2+ In_2In_3+ In_3In_4+ In_4Out_4Out_4+ Out_3Out_3+ Out_2Out_2+ Out_1Out_1+ GND Description Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) Ground return to shield Rev. 3 | Page 6 of 14 | www.onsemi.com CM1235 Ordering Information PART NUMBERING INFORMATION PIN 16 PACKAGE TDFN-16 ORDERING PART NUMBER (LEAD-FREE FINISH) PART MARKING CM1235 CM1235-08DE Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS* PARAMETER Operating Temperature Range Storage Temperature Range Breakdown Voltage (Positive) RATING -40 to +85 -65 to +150 6 UNITS C C V *Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 3 | Page 7 of 14 | www.onsemi.com CM1235 ELECTRICAL OPERATING CHARACTERISTICS SYMBOL PARAMETER VIN IIN IF VESD I/O Voltage Relative to GND Continuous Current through signal pins (IN to OUT) 1000 Hr Channel Leakage Current ESD Protection - Peak Discharge Voltage at any channel input, in system: Contact discharge per IEC 61000-4-2 Standard Residual ESD Peak Current on RDUP (Resistance of Device Under Protection) TA = 25 VIN = 5V C; (SEE NOTE 1) CONDITIONS MIN -0.5 TYP MAX 5.5 UNITS V mA 100 0.1 1.0 A TA = 25 C IEC 61000-4-2 8kV; C; RDUP = 5 TA = 25 See Figure 6. IPP = 1A, TA = 25 C, tP = 8/20S 8 kV IRES 3.0 A VCL Channel Clamp Voltage (Channel clamp voltage per IEC 61000-4-5 Standard) Positive Transients Negative Transients Dynamic Resistance Positive Transients Negative Transients Differential Impedance +9.2 -1.6 IPP = 1A, TA = 25C tP = 8/20S V V RDYN 0.6 0.5 87 103 ZTDR TDR excursion from 100 characteristic impedance transmission line; TR = 200ps; Note 2 Zo Differential Channels pair characteristic impedance TR = 200ps; Note 2 100 Zo Channel-to-Channel Impedance Match (Differential) TR = 200ps; TA = 25C; Note 2 2 % Note 1: All parameters specified at TA = -40 to +85 unless otherwise noted. C C Note 2: Impedance values for deviation from continuous 100 uncompensated differential microstrip, with typical layout as measured. See Figure 7. Rev. 3 | Page 8 of 14 | www.onsemi.com CM1235 Performance Information Graphical Comparison and Test Setup Figure 4 shows that the CM1235 (PicoGuard XS ESD protector) lowers the peak voltage and clamping voltage by 45% across a wide range of loading conditions in comparison to a standard ESD protection device. Figure 5 also indicates that the DUP/ASIC protected by the CM1235 dissipates less energy than a standard ESD protection device. This data was derived using the test setups shown in Figure 6. Figure 4. Normalized VPeak (8KV IEC-61000 4-2 ESD Contact Strike) vs. Loading (RDUP)* Figure 5. Normalized Residual Current into DUP vs RDUP* * RDUP is the emulated Dynamic Resistance (load) of the Device Under Protection (DUP). Rev. 3 | Page 9 of 14 | www.onsemi.com CM1235 Figure 6. Test Setups: Standard Device (Left) and CM1235 (Right) Figure 7. Typical Channel TDR Measured Across Out_x and In_x Per Each Differential Channels Pair (Typical 200ps Incident Rise Time) Rev. 3 | Page 10 of 14 | www.onsemi.com CM1235 CM1235 Application and Guidelines As a general rule, the CM1235 ESD protection array should be located as close as possible to the point of entry of expected electrostatic discharges with minimum PCB trace lengths to the ground planes and between the signal input and the ESD device to minimize stray series inductance. Figure 8. Application of Positive ESD Pulse Between Input Channel and Ground Figure 9. Typical PCB Layout Additional Information See also California Micro Devices Application Note AP209, "Design Considerations for ESD Protection," in the Applications section at www.calmicro.com. Rev. 3 | Page 11 of 14 | www.onsemi.com CM1235 Mechanical Details TDFN-16 Mechanical Specifications, 0.5mm The 16-lead, 1.7x4.0mm, 0.5mm pitch TDFN package dimensions are presented below. PACKAGE DIMENSIONS Package JEDEC No. Leads Dim. Min A A1 A3 b D D2 E E2 e K L # per tape and reel 0.25 0.70 0.00 0.175 0.20 3.90 3.15 1.60 0.45 Millimeters Nom 0.75 0.02 0.200 0.25 4.00 3.20 1.70 0.50 0.50 BSC 0.30 REF 0.30 0.35 Max 0.80 0.05 0.225 0.30 4.10 3.25 1.80 0.55 Min 0.028 0.000 0.007 0.008 0.153 0.124 0.063 0.018 TDFN MO-229C * 16 Inches Nom 0.030 0.001 0.008 0.010 0.157 0.126 0.067 0.020 Max 0.031 0.002 0.009 0.012 0.161 0.128 0.071 0.022 0.020 BSC 0.012 REF 0.010 0.012 0.014 3000 pieces Dimensions for 16-Lead, 0.5mm pitch TDFN package Controlling dimension: millimeters * This package is compliant with JEDEC standard MO-229C with the exception of the D, D2, E, E2, K and L dimensions as called out in the table above. Rev. 3 | Page 12 of 14 | www.onsemi.com CM1235 Tape and Reel Specifications PACKAGE SIZE (mm) 4.00 X 1.70 X 0.75 POCKET SIZE (mm) B0 X A0 X K0 4.30 X 1.90 X 1.20 TAPE WIDTH W 12mm REEL DIAMETER 178mm (7") QTY PER REEL 3000 PART NUMBER CM1235 P0 4mm P1 4mm Rev. 3 | Page 13 of 14 | www.onsemi.com CM1235 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 For additional information, please contact your local Sales Representative Order Literature: http://www.onsemi.com/orderlit ON Semiconductor Website: www.onsemi.com Rev. 3 | Page 14 of 14 | www.onsemi.com |
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